Electronic device with card interface

ABSTRACT

When initializing a card-shaped device inserted in a card interface, operation mode acquiring means incorporated in an electronic device acquires operation mode information, stored in a register file incorporated in the card-shaped device, by a predetermined procedure using a predetermined pin. Operation mode setting means incorporated in the electronic device executes signal assignment on a plurality of data pins peculiar to an operation mode indicated by the acquired operation mode information, thereby switching a data transfer width, and allowing the card-shaped device to operate in the operation mode.

CROSS-REFERENCE TO RELATED APPLICATIONS

This is a continuation of application Ser. No. 11/600,776, filed Nov.17, 2006 (Allowed), now U.S. Pat. No. 7,237,052 which is a continuationof application Ser. No. 11/366,379 filed Mar. 3, 2006 (Allowed); nowU.S. Pat. No. 7,162,561 which is a continuation of application Ser. No.11/001,309 filed Dec. 2, 2004 (Now U.S. Pat. No. 7,051,142); which is acontinuation of 09/799,600 filed Mar. 7, 2001 (Now U.S. Pat. No.6,842,818) and claims the benefit of Japanese Application No.2000-063884, filed Mar. 8, 2000, all of which are incorporated herein byreference.

BACKGROUND OF THE INVENTION

The present invention relates to an electronic device equipped with acard interface, and more particularly to an electronic device suitableto set an operation mode for a card-shaped device connected thereto viathe card interface.

Various types of electronic devices represented by personal computersgenerally have a function of using an IC card (PC card) based on thePCMCIA (Personal Computer Memory Card International Association). The PCcard is used not only as a data storing medium but also for expandingits peripheral function. For example, there are some PC cards thatfunction as a modem card, a network card, a hard disk drive, and atransmitter, etc.

Further, in recent years, IC cards smaller than the PC cards are beingused as well as the PC cards. One of these small IC cards is a smallmemory card that has a flash memory for storing various types of digitaldata represented by image data or music data. As is well known, theflash memory is a non-volatile memory, which is electricallyprogrammable and has its stored contents kept as they are even whenpower supply is interrupted. In such small memory cards having a flashmemory, in general, only one of a plurality of pins is used as a datapin (data line). Accordingly, the small memory cards execute 1-bit datatransfer.

Furthermore, a small memory card called an “SD (Secure Digital) memorycard” is also available. The SD memory card has been developed byMatsushita Electric Industrial Co., Ltd., SanDisk Corporation andToshiba Corporation. The SD memory card has nine signal pins, four ofwhich can be used as data lines. Thus, the SD memory card realizes 4-bitdata transfer, which means that it has a higher data transfer capacitythan the previous small memory card that executes 1-bit data transfer.

As another small card, there is an I/O card having an I/O (Input/Output)interface function. After the appearance of the SD memory card, it isrequested that such a small I/O card and the SD memory card can be usedthrough a common card slot formed in an electronic device (a host) suchas a personal computer, as in the case of the PC cards. To enable asmall memory card, such as the SD memory card, and various types ofsmall I/O cards to be commonly used in an electronic device, it isnecessary to give those cards, for example, the same pin arrangement andthe same shape. Even in this case, however, the following problem willoccur.

In small memory cards, many of the pins provided therein are used asdata lines to enhance their data transfer capacity. For example, in theSD memory card, four of the nine pins are used as data lines asaforementioned. Accordingly, if the same pin arrangement and the sameshape are imparted to the small memory cards and the small I/O cards,many pins are used for data transfer between an electronic device andeach small I/O card. Using a lot of pins as data lines to enhance thedata transfer capacity is effective in the case of a card-shaped devicesuch as a memory card, which does not execute data transfer so often buttransfers a large amount of data atone time. On the other hand, it isnot so important to enhance the data transfer capacity in the case of acard-shaped device such as an I/O card, which executes data transfer(i.e. transaction) many times although it does not transfer a largeamount of data at one time. It is more important to start data transferquickly, i.e. to increase the speed of a response.

BRIEF SUMMARY OF THE INVENTION

The present invention has been developed in light of the above, and aimsto enable an electronic device to set an operation mode for acard-shaped device which is connected thereto when it is used, by acommon procedure irrespective of the type of the card-shaped device, theoperation mode including signal assignment and being peculiar to thecard-shaped device.

To attain the aim, an electronic device according to a first aspectcomprises a card interface, operation mode acquiring means and operationmode setting means. The card interface is designed to be connected to acard-shaped device that has a connector section provided with connectorpins including data pins. The operation mode acquiring means acquireswhen the card interface is connected to the card-shaped device operationmode information of the card-shaped device via a predetermined one ofthe connector pins of the card-shaped device other than the data pins.The operation mode setting means executes signal assignment on each ofthe data pins on the basis of the operation mode information acquired bythe operation mode acquiring means.

In this electronic device, even when a memory card and various types ofI/O cards having different interface functions are made to have a commonpin arrangement, an operation mode including a mode for signalassignment on the data pins of each card (card-shaped device) connectedto the electronic device can be set at an operation mode peculiar to thecard. Moreover, this operation mode setting can be executed irrespectiveof, for example, the type of each card.

An electronic device according to a second aspect further comprisesoperation condition acquiring means and power supply voltage switchmeans. The operation condition acquiring means acquires, via thepredetermined connector pin, an operation condition of the card-shapeddevice, the operation condition including an operating voltage appliedto the card-shaped device. The switch means switches a power supplyvoltage, supplied to the card-shaped device from a predetermined initialvoltage to the operating voltage included in the operation condition.

In this electronic device, an operation condition suitable for acard-shaped device connected to the electronic device can be setirrespective of, for example, the type of the card-shaped device.

In an electronic device according to a third aspect, the operation modesetting means has three functions. A first function is a function ofassigning all the data pins to a data transfer process when theoperation mode information indicates a first operation mode. A secondfunction is a function executed when the operation mode informationindicates the second operation mode, i.e. a function of assigning apredetermined number of ones of the data pins to the data transferprocess, assigning one of the remaining data pins to a process oftransmitting a general purpose signal, assigning another of theremaining data pins to a process of informing the electronic device of astate of the card-shaped device, and assigning yet another of theremaining data pins to a process of transmitting an asynchronousinterrupt signal from the card-shaped device to the electronic device. Athird function is a function executed when the operation modeinformation indicates the third operation mode, i.e. a function ofassigning another predetermined number, larger than the first-mentionedpredetermined number, of ones of the data pins to the data transferprocess, assigning one of the remaining data pins to the process ofinforming the electronic device of the state of the card-shaped device,and assigning another of the remaining data pins to the process oftransmitting an asynchronous interrupt signal from the card-shapeddevice to the electronic device.

In this electronic device, signal assignment suitable for eachcard-shaped device is executed thereon. For example, in a card-shapeddevice having operation mode information that indicates the firstoperation mode, all data pins are assigned to a data transfer process.Thus, the first operation mode is suitable for a card-shaped device thatis required to transfer a large amount of data at high speed, althoughit does not execute data transfer so many times. In a card-shaped devicehaving operation mode information that indicates the second operationmode, a smaller number of data pins are assigned to the data transferprocess, but the remaining data pins are assigned to a process oftransmitting a general purpose signal, a process of informing theelectronic device of a state of the card-shaped device, and a process oftransmitting an asynchronous interrupt signal. Accordingly, the secondoperation mode is suitable for a card-shaped device that is morerequired to transmit a response at high speed than to have a high datatransfer capacity. The second operation mode is most suitable for acard-shaped device such as a modem interface, which needs an audio line,since a general purpose signal line can be used as the audio line. In acard-shaped device having operation mode information that indicates thethird operation mode, no pin is assigned to be used as a general purposesignal line, but the number of data lines increases by one, as comparedwith the device having the operation mode information that indicates thesecond operation mode. Accordingly, the third operation mode is suitablefor a card-shaped device such as a LAN interface, which is required tohave a high data transfer capacity and high-speed response capability.

Additional objects and advantages of the invention will be set forth inthe description which follows, and in part will be obvious from thedescription, or may be learned by practice of the invention. The objectsand advantages of the invention may be realized and obtained by means ofthe instrumentalities and combinations particularly pointed outhereinafter.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

The accompanying drawings, which are incorporated in and constitute apart of the specification, illustrate presently preferred embodiments ofthe invention, and together with the general description given above andthe detailed description of the preferred embodiments given below, serveto explain the principles of the invention.

FIG. 1 is a block diagram illustrating the structure of an informationprocessing system according to the embodiment of the invention;

FIG. 2 is a view illustrating a rough structure of a host 10, and thestructure of an I/O card 20 a as a card 20;

FIGS. 3A and 3B are a flowchart useful in explaining the operation ofthe host 10, focusing on its card initialization process;

FIG. 4 is a view showing the relationship between a command output fromthe host 10 to the card 20, a response output from the card 20 to thehost 10, and a CLK signal;

FIG. 5 is a block diagram useful in explaining download of a devicedriver from the I/O card 20 a to the host 10;

FIG. 6 is a view illustrating an example of a relationship between eachoperation mode employed in an I/O interface mode, and signal assignment;

FIG. 7 is a view illustrating an essential part of a card interface 11for realizing each operation mode; and

FIG. 8 is a block diagram showing an example of a structure in which amaster 15 is incorporated in the host 10.

DETAILED DESCRIPTION OF THE INVENTION

The embodiment of the invention will be described with reference to theaccompanying drawings.

FIG. 1 is a block diagram illustrating the structure of an informationprocessing system according to the embodiment of the invention.

In FIG. 1, a host system (hereinafter referred to as a “host”) 10consists of an electronic device such as a portable personal computer.The host 10 has a card interface 11. The card interface 11 has, forexample, two card slots 11 a and 11 b that enable two small card-shapeddevices (hereinafter referred to simply as “cards”) 20 to be insertedtherein. For the convenience of drawing, FIG. 1 shows a card slotstructure in which two cards 20 arranged in a single plane are inserted.Actually, however, the card slot has a structure that enables two cards20 to be inserted in two vertical stages.

The card interface 11 assigns, to each card 20, a clock (CLK) line, acommand (CMD) line, and four signal lines (DAT[3:0] line) that can beassigned to be used, for example, as data lines. DAT[3:0] indicates foursignal lines DAT[3]-DAT[0]. FIG. 1 does not show a power supply (VDD)line or a ground (GND) line. The CLK line can be commonly used fordifferent cards 20. Therefore, in the embodiment, CLK lines forrespective cards 20 are connected on the card interface 11, therebyenabling the CLK lines to be commonly driven by the host 10. The samecan be said of the VDD and GND lines.

The host 10 includes an initialization basic driver 141 for executing aprocess for initializing each card 20 on the other hand, each card 20has a card register file 21. The card-register file 21 includes a groupof registers that pre-store respective data items such as an operatingvoltage, a card ID, a card address, a card type and an operation mode,etc. for each card 20. The card ID is identification data peculiar toeach card 20. The card address is an address pre-assigned to each card20. The card type indicates whether each card 20 is a memory card or anI/O card. The operation mode will be described later. If each card 20 isan I/O card, it also includes a system I/O register 22. The system I/Oregister 22 pre-stores plug-and-play information (hereinafter referredto as “PnP information”) necessary for realizing a plug-and-playfunction. The PnP information includes data indicating the type of theI/O card, data as to whether or not a device driver peculiar to the I/Ocard is incorporated therein, and data indicating the version of thedriver, if there is one. A Bluetooth interface, a USB (Universal SerialBus) interface, a LAN (Local Area Network) interface, a GPS (GlobalPositioning System) interface and a portable telephone interface, etc.are considered as I/O cards.

FIG. 2 shows a rough structure of the host 10, and the structure of anI/O card 20 a as the card 20. The host 10 has, as well as the cardinterface 11, a CPU (Central Processing Unit) 12, a system memory 13 anda disk storage system 14. The CPU 12 controls the entire host 10. Thesystem memory 13 is used to store various types of data, and programs tobe executed by the CPU 12. The system memory 13 is formed of, forexample, a RAM (Random Access Memory). The disk storage system 14 isformed of, for example, a hard disk drive. The disk storage system 14incorporates various types of device drivers 142, as well as theinitialization basic driver 141. The device drivers 142 include devicedrivers prepared for and peculiar to the respective types of I/O cards.

The I/O card 20 a has a connector section 23 in which nine signal pinswith the numbers 1-9 are arranged. In this embodiment, the signalterminals provided in the connector section 23 are called “signal pins”.However, this name does not necessarily indicate the shape of the signalterminals. In the case of FIG. 2, the signal pins provided in theconnector section 23 are printed pads. A pin, numbered 1, is called “DAT3 (DAT[3])”, and can be assigned to be used, for example, as a dataterminal. A pin, numbered 2, is called “CMD”, and is assigned to be usedas a terminal for transferring a command from the host 10 to the I/Ocard 20 a, and a response to the command from the I/O card 20 a to thehost 10. A pin, numbered 3, is called “GND (Vss1)” and assigned to beused as a first ground signal terminal. A pin, numbered 4, is called“VDD” and assigned to be used as a power signal terminal. A pin,numbered 5, is called “CLK” and assigned to be used as a clock terminal.A pin, numbered 6, is called “GND (Vss2)” and assigned to be used as asecond ground signal terminal. A pin, numbered 7, is called “DAT 0(DAT[6])”, and is assigned to be used as a data terminal. Pins, numbered8 and 9, are called “DAT 1 (DAT[1])” and “DAT 2 (DAT[2])”, respectively,and are assigned to be used as data terminals. The above-mentioned pinarrangement and signal assignment to each pin in the I/O card 20 a arecommonly employed in different types of I/O cards 20 a. Further, thesame can be said of memory cards. In other words, the same pinarrangement and the same signal assignment are employed in all types ofcards 20. However, signals assigned to DAT[3]-DAT[1] (DAT[3:0]) differbetween different types of cards 20. Further, in the case of the I/Ocard 20 a, signals assigned to those pins differ between different typeof I/O cards 20 a. For example, in the case of a memory card,DAT[3]-DAT[0] are assigned to be used as respective bi-directional datalines (data terminals). DAT[3] is also assigned to be used as a carddetection terminal. Signal assignment concerning DAT[3]-DAT[0] in thecase of the I/O card 20 a will be described later.

The I/O card 20 a has a processor module 200. The processor module 200includes a controller 201, a ROM 202, a SRAM (Static RAM) 203, an I/Ointerface 204, an external interface 205 and a memory interface 206. Thecontroller 201 is a microprocessor for controlling the entire I/O card20 a. The ROM 202 stores control programs to be executed by thecontroller 201. A predetermined area of the ROM 22 is assigned to beused as the card register file 21 shown in FIG. 1. The SRAM 203 is usedas a work/buffer memory incorporated in the processor module 200. TheI/O interface 204 is connected to the nine signal pins of the I/O card20 a and serves as an interface between the I/O card 20 a and the host10. The external interface 205 serves as an interface between the I/Ocard 20 a and an external I/O device 60. The memory interface 206 servesas an interface for a flash memory (not shown).

This flash memory is incorporated in the I/O card 20 a and formed of anon-volatile programmable memory. A predetermined area of the flashmemory is assigned to be used as the aforementioned system I/O register22. However, the system I/O register 22 may be incorporated in theprocessor module 200. This structure is applied to an I/O card 20 a thatdoes not always need the flash memory.

Referring now to the flowchart of FIGS. 3A and 3B, a description will begiven of an operation of the embodiment, focusing on its cardinitialization process. Suppose that a card 20 is inserted in one of thecard slots 11 a and 11 b of the card interface 11, when the host is inan ON (power-on) state. In this state, a power signal and a groundsignal are supplied from the host 10 to the card 20 via the VDD line andthe ND line, respectively. As a result, the card 20 reaches a power-onstate. Further, a clock signal is also supplied from the host 10 to thecard 20 via the CLK line. The same state is also reached when the host10 is turned on after the card 20 is inserted into one of the card slotsof the card interface 11. After the card 20 is turned on, theinitialization basic driver 141 incorporated in the host 10 starts thecard initialization process. For facilitating the description, it may bedescribed that the card initialization process is executed by the host10. The card initialization process is also started when a reset commandis output from the host 10 to the card 20 via a CMD line correspondingto the card 20 and incorporated in the card interface 11 (step S0). Itis a matter of course that the initialization basic driver 141 operatesafter it is loaded from the disk storage system 14 to the system memory13.

When starting the card initialization process, a power supply voltagesupplied from the host to the card 20 via the VDD line is set at a valuepredetermined irrespective of the type of the card. This voltage will becalled an “initial voltage”. In this state, in synchronism with a clocksignal supplied via the CLK line, the card 20 executes receipt of acommand and transmission of a response in reply to the command, usingonly the CMD line. This operation is performed irrespective of the cardtype.

The mode for executing the card initialization process is roughlydivided into two modes—a Card identification Mode and a Data TransferMode. In the Card Identification Mode, the card 20 has one of threestates—an Idle State, a Ready State and an Identification State. On theother hand, in the Data Transfer Mode, the card 20 has one of threestates—a Standby State, a Transfer State and an Inactive State.

When the host 10 starts the card initialization process, the operationcondition of a card 20 to be subjected to the card initializationprocess is confirmed (step S1). The step S1 will be described in moredetail.

The host 10 supplies, from the card interface 11 to the card 20 to besubjected to the card initialization process, a first command forconfirming the operation condition of the card 20. More specifically,the host 10 serially supplies the first command to the card 20 via theCMD line between the host 10 and the card 20 in synchronism with a clocksignal on the CLK line.

Upon receiving the first command, the card 20 selects, from the cardregister file 21, an operation condition including its operatingvoltage. The card 20 then serially supplies the host 10 with a response,in which the operation condition is set in reply to the first commandvia the CMD line in synchronism with the clock signal.

FIG. 4 shows the relationship between the command output from the host10 to the card 20, the response output in reply to the command from thecard 20 to the host 10, and the clock signal on the CLK line.

The host 10 receives the response output from the card 20 in reply tothe first command. The response contains the operation condition of thecard 20 including the operating voltage. The host 10 confirms theoperating voltage included in the operation condition of the card 20.These operations are the details of the step S1.

After executing the step S1, the host 10 resets the power supply voltageon the VDD line from the initial voltage to the operating voltage of thecard 20 (step S2). Thus, the power supply voltage on the VDD line isswitched to an operating voltage suitable for the card 20 connected tothe card interface 11 of the host 10. After that, the host 10 supplies,via the CMD line, the card 20 with a second command for informing thecard 20 of the newly set power supply voltage (operating voltage), andconfirming the operation state of the card 20 at this operating voltage(step S2 a). The second command contains, as an argument informationindicating the newly set operating voltage.

The card 20 receives the second command supplied from the host 10. Ifthe card 20 is in a state in which it can be operated by the newly setpower supply voltage, i.e. the operating voltage indicated by thereceived command, the card 20′ supplies the host 10 with a responseindicating its ready state via the CMD line. On the other hand, if thecard is not in that state, the card 20 supplies the host 10 with aresponse indicating its busy state, via the CMD line.

Until receiving the response indicating the ready state of the card 20(step S3), the host 10 supplies the second command to the card 20 (stepS2 a).

Upon receiving the response indicating the ready state of the card 20,the host 10 determines that the card 20 has been sifted from the IdleState to the Ready State.

When determining that the card 20 has reached the Ready State, the host10 acquires a card ID from the card 20 (step S4). The step S4 will bedescribed in detail.

The host 10 supplies the card 20, via the CMD line, with a third commandfor acquiring the card ID from the card 20. The card 20 receives thethird command output from the host 10. In accordance with the receivedthird command, the card 20 acquires its own card ID from the cardregister file 21. After that, the card 20 supplies the host 10 with aresponse, having its own card ID set therein, in reply to the thirdcommand via the CMD line.

The host 10 receives the response output from the card 20 in reply tothe third command. Subsequently, the host 10 extracts the card ID of thecard 20 from the response. This card ID is transferred to an applicationprogram 143 (see FIG. 5) for using the card 20. As a result, the card 20shifts from the Ready State to the Identification State. ThisIdentification State is the final state of the Card Identification Mode.The above-described operations are the details of the step S4.

The host 10 acquires a card address from the card 20 in theIdentification State (step S5). The step S5 will be described in detail.

The host 10 supplies the card 20, via the CMD line, with a fourthcommand for acquiring the card address from the card 20. The card 20receives the fourth command output from the host 10. In accordance withthe received fourth command, the card 20 acquires its own card addressfrom the card register file 21. After that, the card 20 supplies thehost 10 with a response, having its own card address set therein, inreply to the fourth command via the CMD line.

The host 10 receives the response output from the card 20 in reply tothe fourth command. Subsequently, the host 10 extracts the card addressof the card 20 from the response, thereby identifying the card 20. As aresult, the host 10 shifts from the Card Identification Mode to the DataTransfer Mode, while the card 20 reaches the Standby State as theinitial state of the Data Transfer Mode.

In the Standby State, the host 10 selects, using the card addressacquired at the step S5, a card 20 to which the card address is assigned(step S6). The step S6 will be described in detail.

Using the acquired card address, the host 10 outputs a fifth command forselecting the card 20 to which the card address is assigned, to each CMDline on the card interface 11. Then, that one of the cards 20 connectedto the card interface 11 of the host 10 reaches a selected state, towhich the card address indicated by the fifth command from the host 10is assigned, and which is now in a non-selected state. The card 20having reached the selected state supplies the host 10, via the CMDline, with a response indicating that the card itself has been selected.As a result, the card 20 shifts from the Standby State to the TransferState. Upon receiving the response from the card 20, the host 10determines that the card 20 designated by the fifth command has beenselected, and hence the card 20 has shifted to the Transfer State.

At the beginning of the Transfer State, the host 10 reads the card typeand the operation mode of the card 20 selected at the step S6 (step S7).The step S7 will be described in detail.

The host 10 supplies the card 20, via the CMD line, with a sixth commandfor reading the card type and the operation mode of the card 20. Thecard 20 receives the sixth command. In accordance with the receivedsixth command, the card 20 acquires its own card type and operation modefrom the card register file 21. After that, the card 20 supplies thehost 10 with a response, having its own card type and operation mode settherein, in reply to the sixth command via the CMD line.

The host 10 receives the response output from the card 20 in reply tothe sixth command. The host 10 extracts, from the response, the cardtype and operation mode of the card 20 selected at the step S6. Theabove-described operations are the details of the step S7.

In the embodiment, the operation mode of the card 20 differs between acase where the card 20 is a memory card and a case where it is an I/Ocard. In the case of the memory card, the operation mode is only one,i.e. a 4-bit transfer mode. On the other hand, the I/O card has fiveoperation modes, i.e. (1) a 4-bit transfer mode, (2) a 1-bit I/Otransfer mode, (3) a 2-bit I/O transfer mode, (4) a USB I/O transfermode, and (5) a 1394 I/O transfer mode. Each transfer (operation) modefor the I/O-card is collectively called an “I/O interface mode”.Further, the transfer (operation) mode (4-bit transfer mode) for thememory card is called a “memory interface mode”.

When the host 10 has acquired information indicating the card type andthe operation mode of the selected card 20, it determines form the cardtype whether the card 20 is an I/O card or a memory card (step S8). Inaccordance with the determination result and the acquired operationmode, the host 10 executes a step S9 a or S9 b. At the step S9 a or S9b, signal assignment to the card interface 11 is executed. This signalassignment corresponds to signal assignment to each signal pin of thecard 20 (20 a). Further, at the step S9 a or S9 b, a seventh command issupplied to the selected card 20 via a corresponding CMD line. Theseventh command is used for informing the card 20 that its mode can bechanged from the mode set at the start of the initialization process inwhich only the CMD line is used, to an operation (transfer) modepeculiar to the card 20.

Upon receiving the seventh command output from the host 10, the card 20sets its mode at the operation mode peculiar thereto. As a result, thecard 20 can operate in a state in which signal assignment determined bythe peculiar operation mode has been executed on each of the signal pinsDAT[3]-DAT[0]. Thus, in the embodiment, the host 10 can use, wheninitializing a card 20, a mode peculiar to the card 20 as the operationmode including signal assignment to each of the signal pins (dataterminals) DAT[3]-DAT[0] of the card 20, irrespective of, for example,the type of the card 20. In other words, in the embodiment, the host 10can set the operation mode of an I/O card having the same pinarrangement as a memory card, using the same procedure as that for thememory card, irrespective of the type of the I/O card.

Referring now to FIG. 6, a description will be given of the relationshipbetween signal assignment and each operation mode for the I/O card (20a), i.e. each I/O interface mode.

(1) 4-Bit Transfer Mode

In the 4-bit transfer mode, all pins DAT[3]-DAT[0], i.e. DAT[3:0], areassigned to be used as bi-directional data lines. This realizes an I/Ointerface for 4-bit transfer. Signal assignment in this mode is the sameas signal assignment in the only one operation mode for a memory card,i.e. the memory interface mode (4-bit transfer mode).

The 4-bit transfer mode is effective in the case of an I/O card for ahigh-speed communication interface, which transfers a large amount ofdata at one time although it does not execute data transfer (i.e.transaction) many times. In this mode, however, an interrupt line cannotbe assigned, contrast to the case of a 1-bit or 2-bit I/O transfer modedescribed later. Accordingly, the termination of transfer must bedetermined by, for example, polling.

(2) 1-Bit I/O Transfer Mode

In the 1-bit I/O transfer mode, only the pin DAT[0] is assigned to beused as a bi-directional data line. The pin DAT[1] is assigned to beused as a general purpose signal line from the I/O card (20 a) to thehost 10. The pin DAT[2] is assigned to be used as a WAIT/READY line forinforming the host 10 of the state (WAIT/READY) of the I/O card (20 a)in synchronism with a clock signal. The pin DAT[3] is assigned to beused as an interrupt line (INT/WAKE line) for outputting an asynchronousinterrupt signal from the I/O card (20 a) to the host 10.

The asynchronous interrupt signal sent via the INT/WAKE line is one oftwo types of signals. One is an interrupt signal (INT signal) outputfrom the I/O card (20 a) for informing the host 10 of, for example, thetermination of data transfer. The other is an interrupt signal (WAKEsignal) output from the I/O card (20 a) for waking up the host 10 whenthe host is in a power down state or a suspended state, therebyrestoring the host 10 to a normal operation state. This WAKE signal isoutput when the host 10 is in the power down state or the suspendedstate, therefore only the required minimum function of the I/O card (20a) is operable, and this function has detected a predetermined interfacestate. The predetermined interface state indicates, for example, thatstate of an I/O card having a telephone communication function, such asa modem interface, in which the card has received a call signal. In thiscase, the general purpose signal line (DAT[1]) can be used as an audioline.

The 1-bit transfer mode is effective in the case of an I/O card as aninterface, which requires prompt start of data transfer (transaction)since it executes data transfer many times, although it does nottransfer a large amount of data at one time.

(3) 2-Bit I/O Transfer Mode

In the 2-bit I/O transfer mode, the pins DAT[1] and DAT[0] are assignedto be used as bi-directional data lines. The pin DAT[2] is assigned tobe used as a WAIT/READY line as in the 1-bit I/O transfer mode. The pinDAT[3] is assigned to be used as an INT/WAKE line as in the 1-bit I/Otransfer mode. The 2-bit I/O transfer mode differs from the 1-bit I/Otransfer mode in that the pin DAT[1] is assigned to be used as a dataline and not as a general purpose signal line.

The 2-bit I/O transfer mode is effective in the case of an I/O card as aLAN interface, which does not require a general purpose signal line butrequires higher-speed transfer (higher-speed communication) than the I/Ocard that uses the 1-bit I/O transfer mode.

(4) USB I/O Transfer Mode

The USB I/O transfer mode is effective where the I/O card (20 a) is aUSB interface. In this mode, the pins DAT[1] and DAT[0] are assigned tobe used as USB data lines.

(5) 1394 I/O Transfer Mode

The 1394 I/O transfer mode is effective where the I/O card (20 a) is anIEEE (Institute of Electrical and Electronics Engineers, Inc.) 1394interface. In this mode, the four signal lines DAT [3]-DAT[0], i.e.DAT[3:0], are assigned to be used as IEEE 1394 data lines.

In the embodiment, three types of 1-bit I/O cells 71, 72 and 73 areprovided for each signal line DAT[i] (i=3−0) in the card interface 11 ofthe host 10, as is shown in FIG. 7. The cells 71, 72 and 73 havehost-side 1-bit input/output terminals 71 a, 72 a and 73 a and card-side1-bit input/output terminals 71 b, 72 b and 73 b, respectively. The1-bit input/output terminals 71 b, 72 b and 73 b are connected to eachsignal line DAT[i] of the card interface 11. The I/O cell 71 is used forrealizing an interface function peculiar to the operation mode of thecard 20, if the operation mode is a transfer mode, i.e. if it is the4-bit transfer mode, the 1-bit transfer mode or the 2-bit transfer mode.The I/O cell 72 or 73 is each used for realizing an interface functionpeculiar to the operation mode of the card 20, if the operation mode isthe USB I/O transfer mode or the 1394 I/O transfer mode. The interfacefunction of each cell 71, 72 or 73 can be turned on or off from theoutside. The signal line DAT[i] is connected to an end of an activepull-up resister 74 and an end of an active pull-down resister 75. Theresisters 74 and 75 can be turned on and off from the outside.

At the aforementioned step S9 a or S9 b, the initialization basic driver141 in the host 10 turns on only that one of the cells 71, 72 and 73,which corresponds to the operation mode of a card 20 selected at thestep S6, in order to enable the realization of an interface functionpeculiar to the operation mode. Further, the initialization basic driver141 turns on and off the resisters 74 and 75 in accordance with theoperation mode.

As described above, after the host 10 acquires information indicatingthe card type and the operation mode of the card 20 selected at the stepS6 (step S7), it determines from the card type whether the card 20 is amemory card or an I/O card (step S8).

If the card 20 is a memory card, the host 10 executes signal assignmenton the card interface 11 on the basis of the operation mode peculiar tothe memory card and obtained at the step S7 (step 69 b). Further, at thestep S9 b, the host 10 supplies the card 20, via the CMD line, with theseventh command for informing the card 20 that the mode can be changedto the operation mode peculiar to the card 20. After executing the stepS9 b, the host 10 determines that the initialization process on the card20 (memory card) has finished. In this state, the host 10 can beoperated using the card 20 (memory card) (step S16).

On the other hand, if the card 20 is an I/O card, the host 10 executessignal assignment on the card interface 11 on the basis of the operationmode obtained at the step S7, as in the case of the memory card (step S9a). Further, at the step S9 a, the host 10 supplies the card 20 with theseventh command.

Moreover, when the card 20 is an I/O card (20 a), the host 10 determinesthat the initialization process on the I/O card is not completed simplyby executing the step S9 a. This is because when the card 20 is an I/Ocard, configuration settings for realizing a plug-and-play function arenecessary.

To this end, the host 10 reads the contents (PnP information) of thesystem I/O register 22 from the previously selected card 20, i.e. theI/O card 20 a (step S10). The step S10 will be described in detail.

The host 10 supplies the card 20 a, via the CMD line, with an eighthcommand for reading the PnP information from the system I/O register 22in the I/O card 20 a. The card 20 a receives the eighth command outputfrom the host 10. In accordance with the received eighth command, thecard 20 a reads the PnP information from the system I/O register 22.After that, the card 20 a supplies the host 10 with a response havingthe read PnP information set therein, in reply to the eighth command viathe CMD line.

The host 10 receives the response output from the card 20 a in reply ofthe eighth command, and reads, from the response, the PnP informationpeculiar to the I/O card 20 a. The above operations are the details ofthe step S10.

After reading the PnP information peculiar to the I/O card 20 a, thehost 10 refers to it (step S11). From the PnP information, the host 10determines whether or not a device driver 142 a (see FIG. 5) is attachedto the I/O card 20 a (step S12). The device driver 142 a is peculiar tothe I/O card 20 a connected to the card interface 11 of the host 10.Attaching the device driver 142 a to the I/O card 20 a means that thedriver 142 a is stored in the ROM 202 incorporated in the I/O card 20 a.

If the device driver 142 a is attached, the initialization basic driver141 in the host 10 determines whether or not the device driver 142 aattached to the I/O card 20 a has already been downloaded as a devicedriver 142 b (see FIG. 5) into the host 10 (step S13 a). If the devicedriver 142 a is already downloaded as the device driver 142 b, theinitialization basic driver 141 determines whether or not the version ofthe driver 142 b is older than the version indicated by the PnPinformation (step S13 b).

If the device driver 142 b is not downloaded to the host 10, the host 10executes a step S14. The step S14 is executed even when the devicedriver 142 b has been downloaded, if the version of the device driver142 b is older than that indicated by the PnP information. At the stepS14, the device driver 142 a stored in the ROM 202 of the I/O card 20 ais downloaded as the device driver 142 b into the host 10 via a dataline determined by the operation (transfer) mode of the card 20 a, as isshown in FIG. 5. As a result, the next step et seq. are executed underthe control of the device driver 142 b, in place of the initializationbasic driver 141. At the next step, i.e. at a step S15, a systemconfiguration for the I/O card 20 a is automatically set up in the host10 by the downloaded updated device driver 142 b on the basis of the PnPinformation. Thus, in the embodiment, the plug-and-play function can berealized for each card 20 (20 a) connected to the host 10, even whendifferent device drivers corresponding to the respective types of cards20 are not pre-installed in the host 10.

On the other hand, if no device driver 142 a is attached to the I/O card20 a (step S12), the steps S13 a S13 b and S14 are skipped over, and thestep S15 is executed. At the step S15, the system configuration for theI/O card 20 a is automatically set up on the basis of the PnPinformation by that one of the device drivers 142 installed in the host10, which is peculiar to the type of the I/O card 20 a. Further, evenwhen the device driver 142 a is attached to the I/O card 20 a, if adevice driver 142 b, whose version is the same as or more recent thanthe version indicated by the PnP information is already downloaded tothe host 10 (steps S12, S13 a and S13 b), the step S14 is skipped overand the step S15 is executed. At the step S15, automatic configurationsettings for the I/O card 20 a are executed on the basis of the PnPinformation by the device driver 142 b that is already downloaded to thehost 10.

After the automatic configuration settings for the I/O card 20 a finish,the host 10 reaches a state in which it is operable using the I/O card20 a (20) (step S16).

When the host 10 is in the state in which it is operable using the card20 (20 a), an application program 143 incorporated in the host 10 canuse the card 20 (20 a) and execute thereon a process peculiar thereto.

The system shown in FIG. 2 requires, between the system memory 13 of thehost 10 and the card 20 a, a data transfer unit for executing datatransfer. In the prior art, this type of data transfer unit is providedin the card 20 a. In this case, the data transfer unit must access thesystem memory 13 via the card interface 11 under the limitation of adata width (a data transfer width) usable for data transfer and employedin the card interface 11. Therefore, it is difficult to executehigh-speed data transfer between the data transfer unit and the systemmemory 13.

On the other hand, in the embodiment, the data transfer unit is providedin the host 10. The data transfer unit provided in the host 10 is calleda “master”. FIG. 8 illustrates an example of a structure in which amaster is provided in the host 10. In FIG. 8, a master 15 is interposedbetween the system memory 13 and the card interface 11. The I/O card 20a is inserted in a card slot of the card interface 11. The master 15executes data transfer between the system memory 13 and the I/O card 20a. At this time, the master 15 can access the system memory 13 withoutbeing limited by the number of signal lines usable for data transfer andprovided in the card interface 11. The data width of a bus that connectsthe system memory 13 to the master 15 is sufficiently larger than thedata transfer width of the card interface 11. Accordingly, the master 15provided in the host 10 can realize high-speed data transfer betweenitself and the system memory 13, without being limited by a datatransfer width, even if small, between the host 10 and the card 20 a.

There is a case where the user of the host 10 wants to switch the card20 (20 a) selected at the step S6 to another card 20 (20 a). In thiscase, a request for switching the card is supplied from the applicationprogram 143 shown in FIG. 5 to the initialization basic driver 141. Uponreceiving the request, the initialization based driver 141 causes thecurrently selected card 20 (20 a) to reach a non-selected state (stepS17). The step S17 will now be described in detail.

The initialization basic driver 141 supplies the card 20 (20 a), via theCMD line, with a ninth command for causing the currently selected card20 (20 a) to reach a non-selected state. Upon receiving the ninthcommand supplied from the host 10, the card 20 (20 a) shifts to thenon-selected state in accordance with the command.

In the embodiment, the fifth command for selecting a non-selected card20 (20 a) is the same command (a card selecting command) as the ninthcommand for causing a selected card 20 (20 a) to reach a non-selectedstate. When the card selecting command is supplied to a non-selectedcard 20 (20 a), it functions as a command for selecting the card 20 (20a). On the other hand, when the command is supplied to a selected card20 (20 a), it functions as a command for causing the selected card 20(20 a) to reach the non-selected state.

After the initialization basic driver 141 causes the card 20 (20 a)selected at the step S6 to reach a non-selected state at the step S17,the program returns to the step S6. At this time, the initializationbasic driver 141 can select another card 20 (20 a) requested by theapplication program 143.

If the user of the host 10 no more needs to use the card 20 (20 a) andhence wants to shift the card 20 (20 a) to a power-off state, aninactivation command is supplied to the card 20 (20 a) via the CMD lineby the initialization basic driver 141 of the host 10 (step S18). Uponreceiving the inactivation command output from the host 10, the card 20(20 a) shifts from the Transfer State to the Inactive State. In thisstate, the supply of power to the card 20 (20 a) is interrupted.

Additional advantages and modifications will readily occur to thoseskilled in the art. Therefore, the invention in its broader aspects isnot limited to the specific details and representative embodiments shownand described herein. Accordingly, various modifications may be madewithout departing from, the spirit or scope of the general inventiveconcept as defined by the appended claims and their equivalents.

1. A device comprising: connector pins including a plurality of data pins, a command pin, and a power signal pin, such that: only one of the data pins is configured to receive data in a first operation mode, and the plurality of data pins are configured to receive data in a second operation mode; and a set of registers connected to the connector pins, the set of registers storing own operation mode information of the device, the own operation mode information including bus width information which indicates one of the first and second operation modes, wherein: the command pin is configured to receive a first command for reading operation mode information, the operation mode information indicating one of the first and second operation modes; one of the connector pins is configured to transmit the operation mode information in response to the first command; the command pin is configured to receive a second command for reading operation voltage information, the operation voltage information concerning an operation voltage of the device; one of the connector pins is configured to transmit the operation voltage information in response to the second command; and the command pin is configured to receive a third command for setting an operation mode of the device into one of the first and second operation modes.
 2. The device according to claim 1, wherein the command pin is configured to receive power voltage information concerning a power voltage, the power voltage being supplied externally via the power signal pin.
 3. The device according to claim 2, wherein the command pin is configured to transmit a response if the device can operate with the power voltage.
 4. The device according to claim 2, wherein the power signal pin is configured to receive an initial voltage before receiving the power voltage information.
 5. The device according to claim 4, wherein the initial voltage differs from the power voltage.
 6. The device according to claim 1, wherein: the command pin is configured to receive a fourth command for reading an address assigned to the device, and the command pin is configured to transmit the address in response to the fourth command.
 7. The device according to claim 6, wherein: the command pin is configured to receive a fifth command for selecting the device, the fifth command including an address indicating a storage device to be selected, and the device is configured to shift the device to a selected state if the address included in the fifth command is identical to the address assigned to the device.
 8. The device according to claim 1, wherein: the command pin is configured to receive a sixth command for reading identification data, unique to the device, from an electronic device, and the command pin is configured to transmit the identification data in response to the sixth command.
 9. The device according to claim 8, wherein the device is configured to shift the device from a Ready State to an Identification State after transmitting the identification data.
 10. The device according to claim 1, further comprising a memory core being connected to the set of registers.
 11. A device comprising: connector pins including a plurality of data pins, a command pin, and a power signal pin, such that: only one of the data pins is configured to receive data in a first operation mode, and the plurality of data pins are configured to receive data in a second operation mode; and a set of registers connected to the connector pins, the set of registers storing own operation mode information of the device, the own operation mode information including bus width information which indicates one of the first and second operation modes, wherein: the command pin is configured to receive a first command for reading operation mode information, the operation mode information indicating one of the first and second operation modes; one of the connector pins is configured to transmit the operation mode information in response to the first command; the command pin is configured to receive a second command for reading operation voltage information, the operation voltage information concerning an operation voltage of the device; one of the connector pins is configured to transmit the operation voltage information in response to the second command; the command pin is configured to receive a third command for setting an operation mode of the device into one of the first and second operation modes; and the device is configured to set the operation mode in response to the third command.
 12. The device according to claim 11, wherein the command pin is configured to receive power voltage information concerning a power voltage, the power voltage being supplied via the power signal pin.
 13. The device according to claim 12, wherein the command pin is further configured to transmit a response if the device can operate with the power voltage.
 14. The device according to claim 12, wherein the power signal pin is configured to receive an initial voltage from an electronic device before receiving the power voltage information.
 15. The device according to claim 14, wherein the initial voltage differs from the power voltage.
 16. The device according to claim 11, wherein: the command pin is configured to receive a fourth command for reading an address assigned to the device, and the command pin is configured to transmit the address in response to the fourth command.
 17. The device according to claim 16, wherein: the command pin is configured to receive a fifth command for selecting the device, the fifth command including an address indicating a storage device to be selected, and the device is configured to shift the device to a selected state if the address included in the fifth command is identical to the address assigned to the device.
 18. The device according to claim 11, wherein: the command pin is configured to receive a sixth command for reading identification data unique to the device; and the command pin is configured to transmit the identification data in response to the sixth command.
 19. The device according to claim 18, wherein the device is configured to shift the device from a Ready State to an Identification State after transmitting the identification data.
 20. The device according to claim 11, further comprising a memory core being connected to the set of registers. 